Selected Academic Projects


Advanced Operating Systems (C++/xv6/Kernel Development/Scheduling):

  • Used C++ to add a real kernel thread to xv6 (A minimal, instructional UNIX-based OS) using a new system call, Advanced Operating Systems course project, Prof. Nael Abu-Ghazaleh, Spring 2021 (Code | Summery | Report).

  • Used C++ to implement the lottery and stride scheduling, and a system call that tracks the information about the system (information includes number of the process, system calls, and used pages) in xv6 , Advanced Operating System course project, Prof. Nael Abu-Ghazaleh, Spring 2021 (Code | Summery | Report).


Multiprocessor Architecture and Programming (OpenMP/Parallel Programming):


GPU Architecture and Programming (CUDA/OpenMP/OpenCL/Parallel Programming):


Compiler Construction (C++/LLVM/Available Expression Analysis/Liveness Analysis):


High Performance Computing (C++/OpenCL/Parallel Programming):


Data Mining (C++/Data Analysis):

  • Finding influencers in a network using Data Mining Techniques and SNAP Stanford Dataset collections, Data Mining course project, Prof. Vagelis Papalexakis, Spring 2021.

Algorithmic Techniques in Computational Biology (Java/Algorithm Implementation):


Advanced Computer Architecture (C++/Tomasulo/Pipeline/Brach Predictors/Caches):


Information Retrieval and Web Search (C++/Search Engine/Page Rank):


System on Chip Design (Xilinx ISE Design Suite/Synopsis Design Compiler/Post-Layout Simulation/SoC Encounter):

  • Design, Simulation, and implementation of a complex ALU with exciting IP cores in ISE Design Suite (Xilinx), synthesized using Synopsis Design Compiler, System on Chip Design course project, Prof. Shaahin Hessabi, Fall 2017.

  • Post-layout simulation for a complex ALU with SoC Encounter, System on Chip Design course project, Prof. Shaahin Hessabi, Fall 2017.


Testability (Java/Scan Chain/Computer Architecture):

  • Design, Simulation, and implementation of a serial divider at gate level and synthesized it using a Scan Chain, Testability course project, Prof. Shaahin Hessabi, Spring 2017.

  • Implementing a software for simulating the impact of fault and delay on standard combinations logic using JAVA, Testability course project, Prof. Shaahin Hessabi, Spring 2017.

  • Implementing a software for simulating ISCAS combinational circuits at gate level with JAVA, Testability course project, Prof. Shaahin Hessabi, Spring 2017.


Fault Tolerant System Design (C++/Redundancy/Failover/Replication/Checkpointing & Recovery/Graceful Degradation):

  • Analysis of Aging Mitigation Methods in Graphic Processing Units, Advanced Topics in Dependable Computing Systems course project, Prof. Seyed-Ghassem Miremadi, Spring 2017.

  • Analysis of the overhead of crosstalk avoidance codes for reliable data transfer of NoCs, , Advanced Topics in Dependable Computing Systems course project, Prof. Seyed-Ghassem Miremadi, Spring 2017.


Advanced VLSI Design (SoC-Encounter/Power, PDP, & Delay Analysis/Verilog/Modelsim/Synopsis Design Compiler/RTL Desing/HSPICE/PSPICE):

  • Design and implementation of an arbiter circuit, along with determining its minimum die size using SoC-Encounter, Advanced VLSI Design course project, Prof. Shaahin Hessabi, Fall 2016.

  • Finding the optimal W-min for an XOR_XNOR circuit to optimize power, PDP, and delay, Advanced VLSI Design course project, Prof. Shaahin Hessabi, Fall 2016.

  • Designing, simulating, and implementing an arbiter circuit with Verilog, Modelsim, and Synopsis Design Compiler, and examining the effect of optimization constraints on speed and area, Advanced VLSI Design course project, Prof. Shaahin Hessabi, Fall 2016.

  • Designing and simulating NAND gate in RTL logic and examining the effects of pull up resistor on the output load, Advanced VLSI Design course project, Prof. Shaahin Hessabi, Fall 2016.


RTL Design (VHDL/Verilog/ISE DesignMIPS Processor/FPGA Design):

  • Design, Simulation, and Implementation of a Double Precision Floating Point Multiplier with VHDL and ISE Design, VHDL course project, Prof. Naser Mohammadzadeh, Spring 2014.

  • Design, Simulation, and Implementation of MIPS Processor with Verilog, ISE Design Suite, and Xilinx FPGA, Computer Architecture laboratory course, Prof. Naser Mohammadzadeh, Spring 2014.


Artificial Intelligence (C++/Prolog):

  • Design and Implementation of Quoridor Game with Prolog, Artificial Intelligence course project, Prof. Shahrouz Moaven, Spring 2014.

Mahbod Afarin
Mahbod Afarin
PhD Candidate

Mahbod Afarin is a PhD Candidate of computer science and engineering at the University of California Riverside advised by Professor Rajiv Gupta and Professor Nael Abu-Ghazaleh. His research interests include Computer Architecture, Compiler Optimization, and Graph Processing Hardware and Accelerators.