Selected Academic Projects
Advanced Operating Systems (C++/xv6/Kernel Development/Scheduling):
Used C++ to add a real kernel thread to xv6 (A minimal, instructional UNIX-based OS) using a new system call, Advanced Operating Systems course project, Prof. Nael Abu-Ghazaleh, Spring 2021 (Code | Summery | Report).
Used C++ to implement the lottery and stride scheduling, and a system call that tracks the information about the system (information includes number of the process, system calls, and used pages) in xv6 , Advanced Operating System course project, Prof. Nael Abu-Ghazaleh, Spring 2021 (Code | Summery | Report).
Multiprocessor Architecture and Programming (OpenMP/Parallel Programming):
Parallelize matrix multiplication using the OpenMP work-sharing for directive, as specified in the OpenMP API for parallel programming, Multiprocessor Architecture and Programming, Prof. Elaheh Sadredini, Winter 2022 (Code | Summery | Report).
Improving the Performance of Sparse Matrix-Vector Multiplication Using OpenMP, Multiprocessor Architecture and Programming, Prof. Elaheh Sadredini, Winter 2022 (Code | Summery | Report).
GPU Architecture and Programming (CUDA/OpenMP/OpenCL/Parallel Programming):
Implementation of a CUDA-based histogram kernel showcasing the efficient use of atomic operations for parallel computation, GPU Architecture and Programming course project, Prof. Daniel Wong, Fall 2021 (Code | Summery | Report).
Implementation of a tiled matrix multiplication kernel which can support arbitrary-sized matrices using CUDA, GPU Architecture and Programming course project, Prof. Daniel Wong, Fall 2021 (Code | Summery | Report).
Implementing and optimizing the reduction kernel and analyzing basic architectural performance properties using CUDA, GPU Architecture and Programming project, Prof. Daniel Wong, Fall 2021 (Code | Summery | Report).
Improving the performance of Vector Addition program by finding the best basic block size using CUDA, GPU Architecture and Programming course project, Prof. Daniel Wong, Fall 2021 (Code | Summery | Report).
Performance comparison of various GPU programming APIs (OpenMP , CUDA, OpenCL), GPU Architecture and Programming course project, Prof. Daniel Wong, Fall 2021 (Code | Summery | Report).
Compiler Construction (C++/LLVM/Available Expression Analysis/Liveness Analysis):
Implementation of the fundamental available expression analysis and common sub-expression elimination on LLVM using C++, Compiler Construction course project, Prof. Rajiv Gupta, Fall 2021 (Code | Summery).
Implementation of the fundamental liveness analysis as an LLVM pass using C++, Compiler Construction course project, Prof. Rajiv Gupta, Fall 2021 (Code | Summery).
High Performance Computing (C++/OpenCL/Parallel Programming):
Performance optimization of a matrix multiplication program via register and cache reuse using C++, High Performance Computing course project, Prof. Zizhong Chen, Fall 2021 (Code | Summery | Report).
High performance sequential codes for Solving Large Linear Systems, High Performance Computing course project, Prof. Zizhong Chen, Fall 2021 (Code | Summery | Report).
Parallel Sieve of Eratosthenes for Finding All Prime Numbers using Open Message Passing Interface (Open MPI), High Performance Computing course project, Prof. Zizhong Chen, Fall 2021 (Code | Summery | Report).
Data Mining (C++/Data Analysis):
- Finding influencers in a network using Data Mining Techniques and SNAP Stanford Dataset collections, Data Mining course project, Prof. Vagelis Papalexakis, Spring 2021.
Algorithmic Techniques in Computational Biology (Java/Algorithm Implementation):
- Design and implementation of a O(m×n) space, O(m×n×k) time SP Alignment Algorithm for three DNA sequences using JAVA language, Algorithmic Techniques in Computational Biology course project, Prof. Tao Jiang , Spring 2021.
Advanced Computer Architecture (C++/Tomasulo/Pipeline/Brach Predictors/Caches):
Implementing the Tomasulo Speculative Algorithm using C++ language, Advanced Computer Architecture course project, Prof. Daniel Wong, Winter 2020 (Code | Summery | Report).
Design and implementation of a Pipeline Simulator which supports forwarding technique using C++ language, Advanced Computer Architecture course project, Prof. Daniel Wong, Winter 2020 (Code | Summery | Report).
Design and implementation of various branch predictors, including simple 1-bit and 2-bit predictors, as well as correlating (m,n) predictors using C++ language, Advanced Computer Architecture course project, Prof. Daniel Wong, Winter 2020 (Code | Summery | Report).
Design and implementation of a cache, with support for direct-mapped, set-associative, and fully-associative mapping, Advanced Computer Architecture course project, Prof. Daniel Wong, Winter 2020 (Code | Summery | Report).
Information Retrieval and Web Search (C++/Search Engine/Page Rank):
- Design and implementation of a Search Engine which allows users to search related tweets in the cryptocurrency area using Hadoop and Lucene, Information Retrieval and Web Search course project, Prof. Vagelis Hristidis, Winter 2020.
System on Chip Design (Xilinx ISE Design Suite/Synopsis Design Compiler/Post-Layout Simulation/SoC Encounter):
Design, Simulation, and implementation of a complex ALU with exciting IP cores in ISE Design Suite (Xilinx), synthesized using Synopsis Design Compiler, System on Chip Design course project, Prof. Shaahin Hessabi, Fall 2017 (Code | Summery | Report).
End to End ASIC Design and Verification of a Mixed ALU Using Cadence Tools, System on Chip Design course project, Prof. Shaahin Hessabi, Fall 2017 (Code | Summery | Report).
Advanced VLSI Design (SoC-EncounterVerilog/Modelsim/Synopsis Design Compiler /RTL Desing/HSPICE/PSPICE/SoC Encounter/Power, PDP, & Delay Analysis):
Pre and Post-Synthesis Evaluation of a Designs: Functional Verification, Area, Timing, and Power Analysis, Advanced VLSI Design course project, Prof. Shaahin Hessabi, Fall 2016 (Code | Summery | Report).
Physical Design and Layout Flow Using Cadence for Synthesized Digital Circuits, Advanced VLSI Design course project, Prof. Shaahin Hessabi, Fall 2016 (Code | Summery | Report).
Transistor Sizing for Power, Delay, and PDP Optimization Using HSPICE, Advanced VLSI Design course project, Prof. Shaahin Hessabi, Fall 2016 (Code | Summery | Report).
Designing and simulating NAND gate in RTL logic and examining the effects of pull up resistor on the output load, Advanced VLSI Design course project, Prof. Shaahin Hessabi, Fall 2016 (Code | Summery | Report).
Hardware Systems Modeling and Design Methodologies (VHDL/Verilog/ISE Design/MIPS Processor/FPGA Design):
Design, Simulation, and Implementation of a Double Precision Floating Point Multiplier with VHDL and ISE Design, VHDL course project, Prof. Naser Mohammadzadeh, Spring 2014.
Design, Simulation, and Implementation of MIPS Processor with Verilog, ISE Design Suite, and Xilinx FPGA, Computer Architecture laboratory course, Prof. Naser Mohammadzadeh, Spring 2014.
Digital System Design (Xilinx ISE/Modelsim/FPGAs/Verilog):
- Implementation of a Stack-based Processor, Digital System Design Labraturay, I was the Lab Instructor, Summer 2016 (Code | Summery | Report).
- Ternary Content-Addressable Memory (TCAM), Digital System Design Labraturay, I was the Lab Instructor, Summer 2016 (Code | Summery | Report).
- ALU for Complex Numbers, Digital System Design Labraturay, I was the Lab Instructor, Summer 2016 (Code | Summery | Report).
- Universal Asynchronous Receiver Transmitter (UART), Digital System Design Labraturay, I was the Lab Instructor, Summer 2016 (Code | Summery | Report).
- Designing a Digital Incubator Controller, Digital System Design Labraturay, I was the Lab Instructor, Summer 2016 (Code | Summery | Report).
- Multiplier Design using Booth Algorithm, Digital System Design Labraturay, I was the Lab Instructor, Summer 2016 (Code | Summery | Report).
- Behavioral Modeling of a Stack with Push and Pop Operations, Digital System Design, I was the Lab Instructor, Summer 2016 (Code | Summery | Report).
- Dataflow Modeling of a 4-bit Cascadable Comparator & Serial Comparator, Digital System Design, I was the Lab Instructor, Summer 2016 (Code | Summery | Report).
Testability (Java/Scan Chain/Computer Architecture):
Design, Simulation, and implementation of a serial divider at gate level and synthesized it using a Scan Chain, Testability course project, Prof. Shaahin Hessabi, Spring 2017.
Implementing a software for simulating the impact of fault and delay on standard combinations logic using JAVA, Testability course project, Prof. Shaahin Hessabi, Spring 2017.
Implementing a software for simulating ISCAS combinational circuits at gate level with JAVA, Testability course project, Prof. Shaahin Hessabi, Spring 2017.
Fault Tolerant System Design (C++/Redundancy/Failover/Replication/Checkpointing & Recovery/Graceful Degradation):
Analysis of Aging Mitigation Methods in Graphic Processing Units, Advanced Topics in Dependable Computing Systems course project, Prof. Seyed-Ghassem Miremadi, Spring 2017.
Analysis of the overhead of crosstalk avoidance codes for reliable data transfer of NoCs, , Advanced Topics in Dependable Computing Systems course project, Prof. Seyed-Ghassem Miremadi, Spring 2017.
Artificial Intelligence (C++/Prolog):
- Design and Implementation of Quoridor Game with Prolog, Artificial Intelligence course project, Prof. Shahrouz Moaven, Spring 2014.
Mahbod Afarin
PhD Candidate
Mahbod Afarin is a PhD Candidate of computer science and engineering at the University of California Riverside advised by Professor Rajiv Gupta and Professor Nael Abu-Ghazaleh. His research interests include Computer Architecture, Compiler Optimization, and Graph Processing Hardware and Accelerators.